**Assign operator**: blocking and used in writing Combinational logic.

Ex : assign a = b;

**Arithmetic & Assignment operator**: Generally used in combinational loops , generate loops in sequential logic.

Arithmetic Operator types

x = y + z; - Add Operator

x = y - z; - Subtract Operator

x = y / z; - Divide Operator

x = y % z; - Modulo Operator

x = y * z; - Multiply operator

Arithmetic Assignment Operator types

a+=1; i.e, a = a + 1;

a-=1; i.e, a = a - 1;

a/=1; i.e, a = a / 1;

a*=1; i.e, a = a * 1;

a%=4; i.e. a = a % 4;

a*=2; i.e, a = a * a;

**Reduction Operators**: Generally, used in combinational control logic:

logic [3:0] sel;

logic any_sel_hi;

logic all_sel_hi;

logic sel_parity;

any_sel_hi = |sel; // any_sel_hi = sel[3] | sel[2] | sel[1] | sel[0];

all_sel_hi = &sel; // all_sel_hi = sel[3] & sel[2] & sel[1] & sel[0];

sel_parity = ^sel; // sel_parity = sel[3] ^ sel[2] ^ sel[1] ^ sel[0];

inv_sel_parity = ~^sel;

//inv_sel_parity = ~(sel[3] ^ sel[2] ^ sel[1] ^ sel[0]);

inv_any_sel_hi = ~|sel;

//inv_any_sel_hi = ~(sel[3] | sel[2] | sel[1] | sel[0]);

inv_all_sel_hi = ~&sel;

//inv_all_sel_hi = ~(sel[3] & sel[2] & sel[1] & sel[0];

**Relational Operators**: Used for comparison in combinational logic:

logic a;

logic b;

logic c;

assign c = a > b; // c is high/True if a greater than b

assign c = a < b; // c is high/True if a less than b

assign c = a >= b; // c is high/True if a greater than or equal to b

assign c = a <= b; // c is high/True if a less than or equal to b

**Shift Operators**: Logical Shift & Arithmetic Shift.

logic [2:0] a;

logic signed [2:0] b;

logic c, d, e, f;

assign a = 3'b101;

assign b = 3'b101;

// Logical Shift

assign c = a << 1; // shift c by 1 position to left &

// fill the LSB with Zero and remove MSB,

// i.e c = 3'b010;

assign d = a >> 1; // shift a by 1 position to right &

// fill the MSB with Zero and remove LSB,

// i.e c = 3'b010;

//Arithmetic Shift

assign e = b <<< 1; // shift b by 1 position to left &

// fill the LSB with Zero and retain MSB since

// its a signed datatype, i.e e = 3'b110;

assign f = b >>> 1; // shift b by 1 position to right &

// fill the MSB with signed bit and

// remove LSB, i.e f = 3'b110;

// Note that if b were not a Signed datatype,

// results of arithmetic and logical shift would have been same.

// i.e c = e, d = f;

**Conditional Operator**: Used in combinational logic to create Muxes and/or decoder logic.

logic a, b, c, d;

assign c = b ? a : d; // check if b is true if yes, then c = b else c = d.

**Concatenation & Replication Operator**: Used in joining bits to create Bus, concatenation can be on LHS and RHS of assignments. concatenation is treated as packed vector.

logic [4:0] d;

logic [1:0] b,c;

logic a;

// Concatenation

assign d = {a, b, c};

// Replication

d = {5{a}}; // d = {a,a,a,a,a};

// Concatenation + Replication

d = {b,{3{a}}}; // d = {b[1:0], a, a, a};

d = {1{b,c},a}; // d = {b[1:0],c[1:0],a};

**Logical Operator**: Used in comparison of logical expressions. Mainly used to compare and create boolean results. i.e True or false. Arithmetic operators are used if multiple bits are being manipulated.

logic a, b;

logic [3:0] d;

assign a = 1'b1; assign b = 1'b0;

// Result d = 4'h0 if any of a or b is 0.

if(a && b) d = 4'hf else d = 4'h0;

assign a = 1'b1; assign b = 1'b0;

// Result d = 4'hf if any of a or b is 1.

if(a || b) d = 4'hf else d = 4'h0; // Result d = 4'hf;

**Wildcard Operator**: ‘==?’, ‘!=?’. Here operator ‘?’ acts as a wildcard and matches ‘x’ and ‘z’ values from RHS to any value of corresponding bit on LHS.

logic [1:0] c;

logic [1:0] d;

logic e;

assign c = 2'bxz;

assign d = 2'b11;

assign e = (d ==? c); // Result e = 1'b1, as x and z act as wild cards

assign c = 2'b10;

assign d = 2'b1z;

assign e = (d ==? c); // Result e = 1'b0, as z on LHS is not a wild card.

**Streaming Operator**: Streaming operator ‘<<‘ & ‘>>’ are used to pack or unpack the data in specified order. The packing or unpacking can be done on a matching data-type or by type-casting to a particular data-type that match the Widths. If the packed data consists of 4-State type of variable & 2-State type of variable, the result is inferred as 4-state type.

logic a, b, c, d;

logic [3:0] e;

assign e = (>>{a,b,c,d}); // packs a stream of a,b,c,d

{{>>e}}; // unpacks/generates stream of a,b,c,d

{{<<e}}; // unpacks/generates stream of d,c,b,a

(>>{a,b,c,d}) = e; // unpack d=e[0], c=e[1], b=e[2], a=e[3];