# Clock Divider :

In industry, most of clock division happens either through PLL (Phase-locked-loop) in ASIC and through DCM (Digital-Clock-Manger) in FPGAs.

Once clock is available, its possible to have a simple synchronous clock division through few Combinational Gates and D-Flops. Here are few examples of Clock division of equal Duty cycle. Qout (not shown) is the Output of Right-most Flop :

Divide by 2 Counter :

```always_ff @(posedge clk or negedge reset) begin
if(reset)
Q <= 1'b0;
else
Q <= D;
end

assign D = ~Q;
assign Qout = Q;```

Divide by 1.5 Counter :

```always_ff @(posedge clk or negedge reset) begin
if(reset)
Q0 <= 1'b0;
else
Q0 <= D0;
end

assign D0 = ~Q0;

always_ff @(negedge clk or negedge reset) begin
if(reset)
Q1 <= 1'b0;
else
Q1 <= Q0;
end

assign Qout = Q1 | Q0;```

Divide by 3 Counter :

```always_ff @(posedge clk or negedge reset) begin
if(reset)
Q0 <= 1'b0;
else
Q0 <= D0;
end

always_ff @(posedge clk or negedge reset) begin
if(reset)
Q1 <= 1'b0;
else
Q1 <= Q0;
end

always_ff @(negedge clk or negedge reset) begin
if(reset)
Q2 <= 1'b0;
else
Q2 <=  Q1;
end

assign D0 = ~(Q0 & Q1);
assign Qout = Q1 | Q2;```

Divide by 4 Counter :

```always_ff @(posedge clk or negedge reset) begin
if(reset)
Q0 <= 1'b0;
else
Q0 <= D0;
end
assign D0 = ~Q0;

always_ff @(posedge Q0 or negedge reset) begin
if(reset)
Q1 <= 1'b0;
else
Q1 <= D1;
end

assign D1 = ~Q1;
assign Qout = Q1;``` 