As a Digital Designer, often times it is needed to define an interface to communicate to other Design Modules. This communication is defined by a protocol that may involve detection of Rising or Falling edge of a Signal. For E.g Rising edge of request and Falling edge of Ack. In such cases Edge detection logic can be designed as follows:
Rising Edge Detection :
logic rise_edge_sig_a; logic level_sig_a; logic level_sig_a_ff; always_ff @(posedge clk or negedge reset) begin if(!reset) level_sig_a_ff <= 1'b0; else level_sig_a_ff <= level_sig_a; end assign rise_edge_sig_a = level_sig_a & (~level_sig_a_ff);
Falling Edge Detection :
logic fall_edge_sig_b; logic level_sig_b_ff; logic level_sig_b; always_ff @(posedge clk or negedge reset) begin if(!reset) level_sig_b_ff <= 1'b0; else level_sig_b_ff <= level_sig_b; end assign fall_edge_sig_b = (~level_sig_b) & level_sig_b_ff;
Please note that if your intention is to use Level Signal information & convert it into corresponding pulses (Level-to-Pulse Converter) then this design is not a good design fit. This is because the design is Edge detection circuit and relies on edge of the source signal. Therefore, Level Signal information may get lost in the conversion from Level to Pulse.
2 thoughts on “Rise & Fall-Edge Signal Detection:”
already you have always_ff no need to add reset and clk in sensitivity list right
We still need clk and reset in sensitivity list in order to provide information of its clock i.e if its negedge/posedge triggered & if reset is asynchronous.