Delay Module & Shift Registers :

Here are some Design problems that I have encountered at some point in my experience as a Designer and had discussions with others on possible solutions. Please note that there can be multiple approaches to solve the same problem so there are no exclusive right answers.

Question 1: How to detect a signal coming into a logic domain whose clocks are off?

Signal Capture
Signal Capture
Solution :  We can use a Set-Reset flop (signal_ff) whose clock is actually the Signal that we are trying to detect(bit_in). The Set pin of the signal is tied to 1 and Reset is tied to the level detection logic (reset) of flop as shown.Please note that the signal is asynchronous in nature and should be used carefully.

logic bit_in;
logic signal_ff;
logic reset;

always_ff (@posedge bit_in) begin
  if (reset)
    signal_ff <= 1'b0;
    signal_ff <= 1'b1;

assign reset = bit_in & signal_ff;

Question 2: How to detect quickly and efficiently if all bits in a BUS are a) all 0s, b) all 1s, c) any 0s and d) any 0s?

Solution :All zeros can be detected using below logic:
 a) assign allzeros = ~(|bus[7:0]);
 b) assign allones  = (&bus[7:0]);
 c) assign anyzeros = ~(&bus[7:0]);
 c) assign anyones  = (|bus[7:0]);

Question 3: How to design a FIFO or Buffer without explicitly checking Full & Empty conditions ?

This can be done through credit counting logic. 
1. Basically, the fixed number of credits are allocated to the requestor.
2. The requestor agent sends a request to the receiver FIFO/Buffer, its credit is then deducted from credit-counter. 
3. The credit is then incremented whenever FIFO is read out.
4. This Credit counter logic allows FIFO to never get Full as requestor agent is back-pressured whenever credit is not available.

Question 4: How to capture serial stream of Bits and calculate if its 8-bits are odd or even ?

Solution :
In this case, we can use a 8-bit shift Register and simple XOR logic to check if its bits are Odd. The implementation can done as follows :

logic       valid;
logic       bit_in;
logic [7:0] regin;
logic [7:0] regin_ff;
logic       odd_byte;

//8-bit Shift Register:
always_ff (@posedge clk or negedge rst) begin
    regin_ff <= 8'b0;
  elseif (Valid)
    regin_ff <= regin;
    regin_ff <= regin_ff;
assign regin = {regin_ff[6:0] bit_in};

//Odd byte calculation
assign odd_byte = (^regin_ff[7:0]);

Question : How to design a delay Module that has an input valid, data and a parameter that defines how many cycle to delay the data and output valid and data?.

Delay Module
Solution :
  In this case we can use a shift register as discussed above.
  However, key thing to note here is that we don't have to shift data. 
  This can be achieved by :
1. Creating a static ID for each data-packet and shifting the ID instead.
3. The data associated with incoming valid is allocated in any of the empty slots by using Find-First logic and an ID is created.
4. The Valid and ID are then shifted until valid reaches MSB.
5. Whenever MSB Valid is detected, the associated ID is used to index Data. 
6. The data is Muxed out and associated Valid and ID are de-allocated/Invalidated.