Signal Names in Digital Design :

There are various methods of defining signal names in Digital Design. Naming a signal correctly may seem a trivial & underrated task but its important because it often results in faster debug and increases the overall readability of the Code. Defining an intuitive signal could difficult sometimes due to shortage of time at hand or lack of predictability of number of signals needed in the design. Below are few references that can help Designers in faster and intuitive Signal Naming:

Defining Inter-Block Signals : Here Block represents group of Sub-Modules or Modules enclosed in a Top-level Module or Wrapper. Communication between the Blocks may require clock crossing. For Ex. 2 entities within an IP.

Nomenclature : source_destination_signalname_clkdomain_flopStaging

Example 1: logic gen_recv_req_c1ff 
gen   = generator block. 
recv  = receiver block.
req   = signal name (request).
c1    = Clock Domain (optional if same clock domain)
ff    = Staging i.e arriving from a flop.

Defining Intra-Block Signals : These signals have source and destination within the Block but source could be one Submodule & destination could be in another Module within the block. Therefore we can Skip Block name for such cases:

Nomenclature : module1_module2_signalname_staging

Examples:
 
1. logic [7:0] genagt_arb_data_ff

   genagt =  generator agent (Module 1)
   arb    =  Arbiter (Module 2)
   Data   =  Signal Name
   FF     =  Staging i.e Flopped    

2. logic buff_cntrl_sel_comb
   buff  = Buffer (Submodule 1)
   cntrl = Control (Module 2)
   Sel   = Signal Name
   Comb  = Staging

Defining Internal Module/Submodule Signals : These type of signals do not communicate outside as their source and destination are within the Module. For such type of signals, Block, Module, source & destination names can be skipped as communication is between one combinational logic to another combinational logic or Flop and Vice-Versa . Here are few examples :

Nomenclature  : signalname_staging

Examples 1 :
logic eventsel_qual
eventsel  = Event Select (signal name)
qual      = qualified (staging)

Example 2 :
logic stallcyc_ff
stallcyc = Stall Cycle (Signal name)
ff       = flop (Staging)

It is also important to avoid some signal names that could be misleading or unclear, here are examples of unclear Signal Naming :

1. logic arbvalsff; // Difficult to understand without spaces/underscores in between.

2. logic Arb_Val_Sff;// Difficult to grep for some Editors if upper and lower case signals are mixed, also decreases readability.

3. logic arbiter_value_sclock_flopped; // Too long, becomes unreadable.

4. logic arvl_sff; // Too short, becomes unreadable.

5. logic arb_val_ff2; // Numeric Value at the end can cause problems in some Compilers.

6. logic arb_val_inst // '_inst' could be mistaken for a Module Instance

Published by

tachyonyear

Silicon Design Enthusiast.